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IS61NF25632 IS61NF25636 IS61NF51218 IS61NLF25632 IS61NLF25636 IS61NLF51218
256K x 32, 256K x 36 and 512K x 18 FLOW-THROUGH 'NO WAIT' STATE BUS SRAM
ISSI
(R)
PRELIMINARY INFORMATION APRIL 2001
FEATURES
* * * * * * * * * * * * * * * * 100 percent bus utilization No wait cycles between Read and Write Internal self-timed write cycle Individual Byte Write Control Single R/W (Read/Write) control pin Clock controlled, registered address, data and control Interleaved or linear burst sequence control using MODE input Three chip enables for simple depth expansion and address pipelining for TQFP Power Down mode Common data inputs and data outputs CKE pin to enable clock and suspend operation JEDEC 100-pin TQFP, 119 PBGA package Single +3.3V power supply ( 5%) NF Version: 3.3V I/O Supply Voltage NLF Version: 2.5V I/O Supply Voltage Industrial temperature available
DESCRIPTION
The 8 Meg 'NF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 262,144 words by 32 bits, 262,144 words by 36 bits and 524,288 words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -10 10 12 83 Units ns ns MHz
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/26/01 Rev. 00D
1
IS61NF25632 IS61NLF25632
BLOCK DIAGRAM
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
(R)
A [0:17] or A [0:18]
ADDRESS REGISTER
A2-A17 or A2-A18
256Kx32; 256Kx36; 512Kx18 MEMORY ARRAY
MODE A0-A1
BURST ADDRESS COUNTER
A'0-A'1
CLK CKE
CONTROL LOGIC K
WRITE ADDRESS REGISTER
K
DATA-IN REGISTER
CE CE2 CE2 ADV WE BWY X OE ZZ DQa0-DQd7 or DQa0-DQb8 DQPa-DQPd 32, 36 or 18 CONTROL REGISTER
}
CONTROL LOGIC BUFFER
(X=a,b,c,d or a,b)
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
A6 A7 CE CE2 BWd BWc BWb BWa CE2 VCC GND CLK WE CKE OE ADV NC A17 A8 A9
(R)
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ
2
3
4
5
6
7
A6 CE2 A7 NC DQc3 DQc4 DQc6 DQc8 VCC DQd2 DQd3 DQd5 DQd7 NC A5 NC NC
A4 A3 A2 GND GND GND BWc GND NC GND BWd GND GND GND MODE A10 NC
NC ADV VCC NC CE OE A17 WE VCC CLK NC CKE A1 A0 VCC A11 NC
A8 A9 A12 GND GND GND BWb GND NC GND BWa GND GND GND NC A14 NC
A16 CE2 A15 NC DQb6 DQb5 DQb4 DQb2 VCC DQa7 DQa5 DQa4 DQa3 NC A13 NC NC
VCCQ NC NC DQb8 DQb7 VCCQ DQb3 DQb1 VCCQ DQa8 DQa6 VCCQ DQa2 DQa1 NC ZZ VCCQ
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 GND VCC VCC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND GND VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable CE, CE2, CE2 Synchronous Chip Enable OE DQa-DQd MODE VCC GND VCCQ ZZ Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable
A2-A17 CLK ADV BWa-BWd WE CKE
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
3
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
A6 A7 CE CE2 BWd BWc BWb BWa CE2 VCC GND CLK WE CKE OE ADV NC A17 A8 A9
(R)
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ
2
3
4
5
6
7
A6 CE2 A7 DQPc DQc3 DQc4 DQc6 DQc8 VCC DQd2 DQd3 DQd5 DQd7 DQPd A5 NC NC
A4 A3 A2 GND GND GND BWc GND NC GND BWd GND GND GND MODE A10 NC
NC ADV VCC NC CE OE A17 WE VCC CLK NC CKE A1 A0 VCC A11 NC
A8 A9 A12 GND GND GND BWb GND NC GND BWa GND GND GND NC A14 NC
A16 CE2 A15 DQPb DQb6 DQb5 DQb4 DQb2 VCC DQa7 DQa5 DQa4 DQa3 DQPa A13 NC NC
VCCQ NC NC DQb8 DQb7 VCCQ DQb3 DQb1 VCCQ DQa8 DQa6 VCCQ DQa2 DQa1 NC ZZ VCCQ
DQPc DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 GND VCC VCC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND GND VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 DQPa
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable CKE OE DQa-DQd MODE VCC GND VCCQ ZZ DQPa-DQPd 4 Clock Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground solated Output Buffer Supply: +3.3V/2.5V Snooze Enable Parity Data I/O CE, CE2, CE2 Synchronous Chip Enable
A2-A17 CLK ADV BWa-BWd WE
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
A6 A7 CE CE2 NC NC BWb BWa CE2 VCC GND CLK WE CKE OE ADV NC A18 A8 A9
(R)
PIN CONFIGURATION
119-pin PBGA (Top View) and 100-Pin TQFP
1 A VCCQ B NC C NC D DQ9 E NC F VCCQ G NC H DQ12 J VCCQ K NC L DQ14 M VCCQ N DQ16 P NC R NC T NC U VCCQ
2
3
4
5
6
7
A6 CE2 A7 NC DQ10 NC DQ11 NC VCC DQ13 NC DQ15 NC DQP2 A5 A10 NC
A4 A3 A2 GND GND GND BWb GND NC GND NC GND GND GND MODE A11 NC
NC ADV VCC NC CE OE A17 WE VCC CLK NC CKE A1 A0 VCC NC NC
A8 A9 A12 GND GND GND NC GND NC GND BWa GND GND GND NC A14 NC
A16 CE2 A15 DQP1 NC DQ7 NC DQ5 VCC NC DQ3 NC DQ2 NC A13 A18 NC
VCCQ NC NC NC DQ8 VCCQ DQ6 NC VCCQ DQ4 NC VCCQ NC DQ1 NC ZZ VCCQ
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A11 A12 A13 A14 A15 A16 A17
NC NC NC VCCQ GND NC NC DQ9 DQ10 GND VCCQ DQ11 DQ12 GND VCC VCC GND DQ13 DQ14 VCCQ GND DQ15 DQ16 DQP2 NC GND VCCQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A10 NC NC VCCQ GND NC DQP1 DQ8 DQ7 GND VCCQ DQ6 DQ5 GND GND VCC ZZ DQ4 DQ3 VCCQ GND DQ2 DQ1 NC NC GND VCCQ NC NC NC
512K x 18
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable CE, CE2, CE2 Synchronous Chip Enable OE DQ1-DQ16 MODE VCC GND VCCQ ZZ DQP1-DQP2 Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable Parity Data I/O DQP1 is parity for DQ1-8; DQP2 is parity for DQ9-16
A2-A18 CLK ADV BWa-BWb WE CKE
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
5
IS61NF25632 IS61NLF25632
STATE DIAGRAM
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
(R)
READ BEGIN READ WRITE DS READ DS WRITE BEGIN WRITE
READ
WRITE
READ
BURST DS
DESELECT BURST
BURST
WRITE
DS BURST READ WRITE
DS BURST WRITE
BURST
BURST
READ
SYNCHRONOUS TRUTH TABLE(1)
Operation Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Address Used N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address CS1 X L X L X L X L X X CS2 X H X H X H X H X X CS2 X L X L X L X L X X ADV H L H L H L H L H X WE X H X H X L X L X X BWx X X X X X L L H H X OE X L L H H X X X X X CKE L L L L L L L L L H CLK

Notes: 1. "X" means don't care. 2. The rising edge of clock is symbolized by 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE).
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
(R)
ASYNCHRONOUS TRUTH TABLE(1)
Operation Sleep Mode Read Write Deselected ZZ H L L L L OE X L H X X I/O STATUS High-Z DQ High-Z Din, High-Z High-Z
Notes: 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP WE H L L L L BWa X L H L H BWb X H L L H
Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE (x32/x36)
Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP WE H L L L L L L BWa X L H H H L H BWb X H L H H L H BWc X H H L H L H BWd X H H H L L H
Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
7
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
3rd Burst Address A1 A0 11 10 01 00
(R)
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Value Unit -10 to +85 C -65 to +150 C 1.6 W 100 mA -0.5 to VCCQ + 0.3 V -0.3 to 4.6 V
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
VCCQ 3.3V 5% 2.5V 5% 3.3V 5%
(R)
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 5% 3.3V 5% 3.3V 5%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
2.5V Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND VIN VCC
(1)
3.3V Max. -- 0.4 Min. 2.4 -- 2.0 -0.3 -5 -5 Max. -- 0.4 VCC + 0.3 0.8 5 5 Unit V V V V A A
Test Conditions IOH = -4.0 mA (3.3V) IOH = 1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V)
Min. 2.0 -- 1.7 -0.3 -5 -5
VCC + 0.3 0.7 5 5
GND VOUT VCCQ, OE = VI
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-10 MAX Symbol Parameter ICC AC Operating Supply Current Test Conditions Device Selected, Com. OE = VIH, ZZ VIL, IND. All Inputs 0.2V OR VCC - 0.2V, Cycle Time tKC min. x18 300 350 x32/36 300 350 Unit mA
ISB
Standby Current Device Deselected, COM. TTL Input VCC = Max., Ind. All Inputs 0.2V OR VCC - 0.2V, ZZ VIL, f = Max. Standby Current Device Deselected, Com. CMOS Input VCC = Max., Ind. VIN GND + 0.2V or VCC - 0.2V f=0
80 90
80 90
mA
ISBI
20 25
20 25
mA
Note: 1. MODE pin has an internal pullup and should be tied to Vcc or GND. It exhibits 30 A maximum leakage current when tied to GND + 0.2V or Vcc - 0.2V.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
9
IS61NF25632 IS61NLF25632
CAPACITANCE(1,2)
Symbol CIN COUT
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
Max. 6 8 Unit pF pF
(R)
Parameter Input Capacitance Input/Output Capacitance
Conditions VIN = 0V VOUT = 0V
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V.
3.3V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2
3.3V I/O OUTPUT LOAD EQUIVALENT
317
ZO = 50 OUTPUT
+3.3V
OUTPUT
50
351
5 pF Including jig and scope
1.5V
Figure 1
Figure 2
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
(R)
2.5V I/O AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4
2.5V I/O OUTPUT LOAD EQUIVALENT
1,667
ZO = 50 OUTPUT
+2.5V
OUTPUT
50
1,538
1.25V
5 pF Including jig and scope
Figure 3
Figure 4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
11
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
-10 Min. Max. -- 12 3 3 -- 3 2.5 -- -- 0 -- 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 83 -- -- -- 10 -- -- 6 3.5 -- 4 -- -- -- -- -- -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(R)
READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol fmax tKC tKH tKL tKQ tKQX(2) tKQLZ tOEQ tOELZ(2,3) tOEHZ tAS tWS tCES tSE tAVS tDS tAH tHE tWH tCEH tADVH tDH
(2,3) (2,3) (2,3)
Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock EnableHold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time
tKQHZ
Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2.
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
Min. -- 2 2 2 0 Max. 10 -- -- -- -- Unit mA cycle cycle cycle ns
(R)
SLEEP MODE ELECTRICAL CHARACTERISTICS
Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current Conditions ZZ Vih
SLEEP MODE TIMING
K
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All Inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z Don't Care
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
13
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
(R)
READ CYCLE TIMING
tKH tKL
Clock
tADVS tADVH
ADV
tKC
tAS tAH
A17 - A0 or A18 - A0 A1 A2 A3
tWS tWH
WE
tSE tHE
CKE
tCES tCEH
CE
OE
tOEQ tOEHZ
Data Out
Q1-1
tOEHZ
tDS
Q2-1
tKQ tKQHZ
Q2-2 Q2-3 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4
NOTES: WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care Undefined
14
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
(R)
WRITE CYCLE TIMING
tKH tKL
Clock
tKC
ADV
A17 - A0 or A18 - A0
A1
A2
A3
WE
tSE tHE
CKE
CE
OE
tDS
Data In
D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 D3-2
tDH
D3-3 D3-4
tOEHZ
Data Out
Q0-4
NOTES: WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L
Don't Care Undefined
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
15
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
tCH tCL
(R)
SINGLE READ/WRITE CYCLE TIMING
Clock
tCES tCEH tCYC
CKE
Address
A1
A2
A3
A4
A5
A6
A7
A8
A9
WRITE
CS
ADV
OE
tOE tLZOE
Data Out
Q1
tDS tDH
Q3
Q4
Q6
Q7
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
D5
Don't Care Undefined
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
tCH tCL
(R)
CKE OPERATION TIMING
Clock
tCES tCEH tCYC
CKE
Address
A1
A2
A3
A4
A5
A6
WRITE
CS
ADV
OE
tCD tLZC tHZC
Data Out
Q1
tDS tDH
Q3
Q4
Data In
NOTES: WRITE = L means WE = L and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
D2
Don't Care Undefined
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
17
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
tCH tCL
(R)
CS OPERATION TIMING
Clock
tCES tCEH tCYC
CKE
Address
A1
A2
A3
A4
A5
WRITE
CS
ADV
OE
tOE tLZOE tHZC tCD tLZC
Data Out
Q1
Q2
tDS tDH
Q4
Data In
D2
NOTES: WRITE = L means WE = L and BWx = L CS = L means CS1 = L, CS2 = H and CS2 = L CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L and CS2 = L
D5
Don't Care Undefined
18
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
Order Part Number IS61NF25632-10TQI IS61NF25632-10BI IS61NF25636-10TQI IS61NF25636-10BI IS61NF51218-10TQI IS61NF51218-10BI
(R)
ORDERING INFORMATION Commercial Range: 0C to +70C
Frequency 256Kx32 10 256Kx36 10 512Kx18 10 IS61NF51218-10TQ IS61NF51218-10B TQFP PBGA IS61NF25636-10TQ IS61NF25636-10B TQFP PBGA IS61NF25632-10TQ IS61NF25632-10B TQFP PBGA Order Part Number Package
Industrial Range: -40C to +85C
Frequency 256Kx32 10 256Kx36 10 512Kx18 10 TQFP PBGA TQFP PBGA TQFP PBGA Package
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01
19
IS61NF25632 IS61NLF25632
IS61NF25636 IS61NF51218 IS61NLF25636 IS61NLF51218
ISSI
Order Part Number IS61NLF25632-10TQI IS61NLF25632-10BI IS61NLF25636-10TQI IS61NLF25636-10BI IS61NLF51218-10TQI IS61NLF51218-10BI
(R)
ORDERING INLFORMATION Commercial Range: 0C to +70C
Frequency 256Kx32 10 256Kx36 10 512Kx18 10 IS61NLF51218-10TQ IS61NLF51218-10B TQFP PBGA IS61NLF25636-10TQ IS61NLF25636-10B TQFP PBGA IS61NLF25632-10TQ IS61NLF25632-10B TQFP PBGA Order Part Number Package
Industrial Range: -40C to +85C
Frequency 256Kx32 10 10 256Kx36 10 10 512Kx18 10 10 TQFP PBGA TQFP PBGA TQFP PBGA Package
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
20
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D 04/26/01

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